An electronic system typically has a power supply that is selected to provide a sufficient amount of power to the system under all operating conditions. The size of the power supply is determined by the maximum peak power used by the electronic system because the maximum peak power condition is a condition that needs to be handled by the electronic system. The maximum peak power (also called peak power or worst case power) required by the electronic system can sometimes be a relatively large number as compared with average power required by the electronic system.
High peak power typically results in the need for power supplies that are larger, heavier, more costly, and less energy efficient, which is a disadvantage. Moreover, other more costly electronic components may need to be used for an electronic system with a relatively high peak power characteristic. For example, a higher peak power characteristic may require the need for more bypass capacitors and larger bypass capacitors.
In addition, operating an electronic system at or near peak power is typically disadvantageous. When the system operates at or near worst-case conditions, the operating temperature of the circuits and components in the system is generally elevated. If the system operates at or near the worst-case operating condition for an extended period of time, the elevated temperatures may tend to cause failures in the system resulting in a less reliable system. To help to avoid such failures, cooling systems can be included in the electronic systems. Cooling systems, however, typically add cost, complexity, and weight to a system. If fans are added to cool a system, that can result in noise and in power use by the fan. Heat sinks sometimes mean larger packages are required to accommodate the heat sink and to allow for ventilation.
Operating an electronic system at maximum peak power may also increase the amount of electromagnetic interference ("EMI") generated over time, which could increase amount of EMI shielding required for the electronic system.
For electronic systems that use complementary metal oxide semiconductor ("CMOS") logic, the power drawn by a circuit or component is shown in Equation 1 below, wherein P is the power drawn by the system, f is the operating frequency or data rate, C is the capacitance, and V is the voltage swing of the voltage output of the circuit. EQU P+fCV.sup.2 (Equation 1)
As shown by Equation 1, the power drawn by a CMOS logic gate is directly proportional to the frequency or data rate of the logic gate. Thus, the greater the rate, the greater the power drawn by the logic gate for a given capacitance and voltage swing. Equation 1 also indicates that, for a given capacitance, a maximum amount of power is drawn by a CMOS logic gate when the voltage swing is a maximum amount (e.g., when changing logic states) in every cycle and the logic gate is operating at a maximum data rate.
CMOS logic gates are often used within an integrated device and between integrated devices to drive relatively high capacitance lines. For example, CMOS logic gates are often used in integrated circuits as output buffers to drive, for example, data bus lines. If these gates switch logic states at the maximum data rate, then large amounts of power may be drawn by the system. Even though the data pattern that corresponds to this is atypical, the cooling mechanism must be designed to handle this event. Otherwise, failures in the electronic system could occur as the result of the elevated temperatures. But, as stated above, cooling systems can add cost, complexity, and weight to a system.
FIGS. 1 and 2 show how prior art circuitry can operate at maximum peak power for a given clock frequency. FIG. 1 is a diagram of prior art circuitry 19 that includes signal line 3, which is one of the "N" signal lines of data bus 4. Each of the signal lines of data bus 4 includes buffers 5 and 10. Signal line 3 includes parasitic capacitance represented by capacitors 21 and 22. Waveforms 28, 30, and 35 represent possible data patterns at respective points 18, 20, and 25 of a waveform that is transmitted along signal line 3.
FIG. 2 is a table showing the toggling of signals along signal line 3. Column 40 shows a two-period snapshot of possible waveforms at point "A" (reference number 18). Column 42 shows the number of signal transitions--i.e., toggles--for the possible respective waveforms at point "A." Column 46 shows a two-period snapshot--i.e., a two-bit snapshot--of possible waveforms at point "B" (reference number 20). Column 48 sets forth the number of signal transitions, for the respective waveforms at point B. Column 50 shows a two-period snapshot of possible waveforms at point "C" (reference number 25). Column 52 refers to the number of toggles for the respective waveforms at point C.
Column 54 of FIG. 2 sets forth the sum of the toggles occurring at points B and C along signal line 3. The sum in column 52 is for the same wave front traveling through points B and C along signal line 3. The sum of the toggles at points B and C is zero for the waveforms that have no signal transitions--i.e., the waveforms that stay at zero or a logic one. For the waveforms that toggle from logic one to a logic zero, or from a logic zero to a logic one, the sum of the toggles at points B and C is two because there is one toggle at point B and another toggle at point C.
For a given waveform, when the sum in column 54 is two, that means that the circuitry shown in FIG. 1 is operating at maximum peak power. For CMOS circuitry, power is consumed during the signal transitions. The more signal toggles there are, the more power consumed by the circuitry. Thus, when the sum of the toggles at buffered areas B and C totals two, that means that the maximum peak power is being consumed for a given clock frequency.